1. Field of the Invention
The present invention relates to a method of forming a gate spacer on a semiconductor wafer.
2. Description of the Prior Art
During a semiconductor process, the gate spacer isolates the gate, drain and source electrically. The spacer and gate can together be used as a mask during the heavy doping process of the drain and source. In general, formation of the spacer is accomplished by first depositing an undoped silicate glass (USG) dielectric layer then removing part of the USG dielectric layer by an etching process. The remaining USG dielectric layer on the side-wall of the gate is the spacer.
Please refer to FIG. 1 to FIG. 3. FIGS. 1 to 3 are schematic diagrams of a method of forming a spacer 12 of a gate 18 on a semiconductor wafer 10 according to the prior art. As shown in FIG. 1, a semiconductor wafer 10 comprises a Si substrate 14, two field oxide regions 16,17 formed on the Si substrate 14 for electrical isolation, and a gate 18 formed on the field oxide region 17. The gate 18 protrudes from the surface of the semiconductor wafer 10 such that the top end of the gate 18 is higher than the top end of the field oxide region 16. Please refer to FIG. 2. To form the spacer 12, a USG dielectric layer 20 is first formed on the semiconductor wafer 10 by atmospheric pressure chemical vapor deposition (APCVD) . The resultant USG dielectric layer 20 covers both the gate 18 and field oxide region 16. However, the top end of the gate 18 is higher than the top end of the field oxide region 16, it causes a problem with step coverage during the APCVD process. Finally, the thickness (a) of the USG dielectric layer 20 above the gate 18 is larger than the thickness (b) of the USG dielectric layer 20 above the field oxide region 16.
Please refer to FIG. 3. An anisotropic etching process is performed on the semiconductor wafer. The USG dielectric layer 20 is partially removed. The remaining parts of the USG dielectric layer 20 on the side-wall of the gate 18 form the two spacers 12 of the gate 18. However, if the USG dielectric layer 20 above the gate 18 is to be removed completely, over-etching will occur on the USG dielectric layer 20 above the field oxide region 16. This may reduce the thickness of the field oxide region 16 and degrade electrical isolation efficiency. In FIG. 3, the dashed line indicates the top end of non-over-etched field oxide region 16 and the solid line indicates the top end of the over-etched field oxide region 16. The thickness difference between the non-over-etched field oxide region 16 and the over-etched field oxide region 16 is (a-b).